Physical Sciences and Mathematics Commons^™

Computing Specificity, Ronald Loui, J. Norman, K. Stiefvater, A. Merrill, A. Costello, J. Olson

All Computer Science and Engineering Research

This note reports on an effort to implement a version of Poole's rule for specificity. Relatively, efficient implementation relies on correcting and improving a pruning lemma of Simari-Loui [92]. This in turn requires revision of Poole's specificity concept. The resulting system is a usable knowledge representation system with first-order-language and defeasible reasoning. Sample input and output are included in an appendix. It is a good candidate for multiple inheritance applications; it is useful for planning, but limited by the underlying search for plans.

Wright State University College Of Engineering And Computer Science Bits And Pcs Newsletter, Volume 8, Number 8, November 1992, College Of Engineering And Computer Science, Wright State University

BITs and PCs Newsletter

A fourteen page newsletter created by the Wright State University College of Engineering and Computer Science that addresses the current affairs of the college.

Wright State University College Of Engineering And Computer Science Bits And Pcs Newsletter, Volume 8, Number 7, October 1992, College Of Engineering And Computer Science, Wright State University

BITs and PCs Newsletter

A ten page newsletter created by the Wright State University College of Engineering and Computer Science that addresses the current affairs of the college.

Process And Policy: Resource-Bounded Non-Demonstrative Reasoning, Ronald P. Loui

All Computer Science and Engineering Research

This paper investigates the appropriateness of formal dialectics as a basis for non-monotonic and defeasible reasoning that takes computational limits seriously. Rules that can come into conflict should be regarded as policies, which are inputs to deliberative processes. Dialectical protocols are appropriate for such deliberations when resources are bounded and search is serial. AI, it is claimed here, is now perfectly positioned to correct many misconceptions about reasoning that have resulted from mathematical logic's enormous success in this century: among them (1) that all reasons are demonstrative, (2) that rational belief is constrained, not constructed, (3) that process and disputation …

Interaction Of Profiled Light With Contrapropagating Acoustic Waves: Fourier Transform Approach, Partha P. Banerjee, Chen-Wen Tarn, Jaw-Jueh Liu

Electrical and Computer Engineering Faculty Publications

A straightforward Fourier-transform approach is employed to investigate acousto-optic interaction between an input optical beam with arbitrary profile and contrapropagating cw sound in the Bragg regime. The process can be analyzed in terms of the simultaneous scattering of light by the two sound waves in the interaction region. Analytic expressions for the equivalent transfer functions are obtained and the scattered light profiles are plotted.

Packet Routing In Networks With Long Wires, Ronald I. Greenberg, H.-C. Oh

Computer Science: Faculty Publications and Other Works

In this paper, we examine the packet routing problem for networks with wires of differing length. We consider this problem in a network independent context, in which routing time is expressed in terms of “congestion” and “dilation” measures for a set of packet paths. We give, for any constant ε > 0, a randomized on-line algorithm for routing any set of N packets in O((Clg^ε(Nd)+Dlg(Nd))/lglg(Nd)) time, where C is the maximum congestion and D is the length of the longest path, both taking wire delays into account, and d is the longest path in terms of number of wires. We also …

Separating Structure From Function In The Specification And Design Of Distributed Systems, Kenneth J. Goldman

All Computer Science and Engineering Research

A distributed system is viewed as a collection of functional components and a unifying structure that defines relationships among the components. In the paper, we advocate a particular approach to distributed system specification and design in which the structure of a distributed system is specified separately from the functional components. This permits one to reason about individual functional components in isolation, and encourages one to make explicit not only the input/output behavior of the functional components but also the logical placement of these components within the overall structure of the system. We describe a new software tool for the specification, …

Wright State University College Of Engineering And Computer Science Bits And Pcs Newsletter, Volume 8, Number 6, September 1992, College Of Engineering And Computer Science, Wright State University

BITs and PCs Newsletter

An eight page newsletter created by the Wright State University College of Engineering and Computer Science that addresses the current affairs of the college.

Dna Mapping Algorithms: Strategies For Single Restriction Enzyme And Multiple Restriction Enzyme Mapping, Will Gillett

All Computer Science and Engineering Research

An approach to high-resolution restriction-fragment DNA mapping, known as Multiple-Restriction-Enzyme mapping (MRE mapping), is present. This approach significantly reduces the uncertainty of clone placement by using clone ends to synchronize the position in of clones within different maps, each map being constructed from fragment-length data produced by digestion of each clone with a specific restriction enzyme. Maps containing both fragments-length data and clone-end data are maintained for each restriction enzyme, and synchronization between two such maps is achieved by requiring them to have "compatible" clone-end map projections. Basic definitions of different kinds of maps, such as restriction sites maps, restriction …

Can Pac Learning Algorithms Tolerate Random Attribute Noise?, Sally A. Goldman, Robert H. Sloane

All Computer Science and Engineering Research

This paper studies the robustness of pac learning algorithms when the instances space is {0,1}n, and the examples are corrupted by purely random noise affecting only the instances (and not the labels). In the past, conflicting results on this subject have been obtained -- the "best agreement" rule can only tolerate small amounts of noise, yet in some cases large amounts of noise can be tolerated. We show that the truth lies somewhere in between these two alternatives. For uniform attribute noise, in which each attribute is flipped independently at random with the same probability, we present an algorithm that …

Analysis Of Multifrequency Dispersive Optical Bistability And Switching In Nonlinear Ring Cavities With Large Medium-Response Times, Pawel Pliszka, Partha P. Banerjee

Electrical and Computer Engineering Faculty Publications

Using a simple model of a ring cavity comprising a cubically nonlinear medium, we analyze dispersive optical bistability in the presence of more than one spectral component. We show the phenomenon of so-called competition for resonance. In addition to presenting cavity characteristics for the cases of two and three different frequencies, we also discuss the general method for finding steady-state solutions and checking their stability. A simple and efficient algorithm, based on a relaxation method, is devised to find steady-state solutions satisfying appropriate boundary conditions. The relaxation dynamics is physically related to a finite response time of the medium.

The 3-Tier Structured Access Protocol To Control Unfairness In Dqdb Mans, Lakshmana N. Kumar, Andreas D. Bovopoulos

All Computer Science and Engineering Research

This paper addresses the unfairness problem appearing in 802.6-based DQDB MANs. Traffic load demand is characterized as low (below 0.4 of the channel capacity), normal (from 0.4 to 0.9 of the channel capacity) or heavy (greater than 0.9 of the channel capacity). At low loads the 802.6 protocol is acceptably fair. At normal loads, however, the protocol performance is markedly unfair. The unfairness is related to the latency in transporting a request. At heavy loads the unfairness is both latency-related and flooding-related. In this paper, both types of unfairness are carefully analyzed. As a control measure, a 3-Tier Structured Access …

Wright State University College Of Engineering And Computer Science Bits And Pcs Newsletter, Volume 8, Number 5, May 1992, College Of Engineering And Computer Science, Wright State University

BITs and PCs Newsletter

A six page newsletter created by the Wright State University College of Engineering and Computer Science that addresses the current affairs of the college.

Wright State University College Of Engineering And Computer Science Bits And Pcs Newsletter, Volume 8, Number 4, April 1992, College Of Engineering And Computer Science, Wright State University

BITs and PCs Newsletter

An eight page newsletter created by the Wright State University College of Engineering and Computer Science that addresses the current affairs of the college.

Wright State University College Of Engineering And Computer Science Bits And Pcs Newsletter, Volume 8, Number 3, March 1992, College Of Engineering And Computer Science, Wright State University

BITs and PCs Newsletter

An eight page newsletter created by the Wright State University College of Engineering and Computer Science that addresses the current affairs of the college.

Implementation And Analysis Of Np-Complete Algorithms On A Distributed Memory Computer, Joel S. Garmon

Theses and Dissertations

The purpose of this research is to explore methods used to parallelize NP-complete problems and the degree of improvement that can be realized using different methods of load balancing. A serial and four parallel A* branch and bound algorithms were implemented and executed on an Intel iPSC/2 hypercube computer. One parallel algorithm used a global, or centralized, list to store unfinished work and the other three parallel algorithms used a distributed list to store unfinished work locally on each processor. the three distributed list algorithms are: without load balancing, with load balancing, and with load balancing and work distribution. The …

Boolean Reasoning And Informed Search In The Minimization Of Logic Circuits, James J. Kainec

Theses and Dissertations

The minimization of logic circuits has been an important area of research for more than a half century. The approaches taken in this field, however, have for the most part been ad hoc. Boolean techniques have been employed to manipulate formulas, but not to perform symbolic reasoning. Boolean equations are employed principally as icons; they are never solved. The first objective of this dissertation is to apply Boolean reasoning systematically and uniformly to the minimization problem. Boolean reasoning entails the reduction of systems of Boolean equations to a single equation; the single equation is an abstraction, independent of the form …

Wright State University College Of Engineering And Computer Science Bits And Pcs Newsletter, Volume 8, Number 2, February 1992, College Of Engineering And Computer Science, Wright State University

BITs and PCs Newsletter

An eight page newsletter created by the Wright State University College of Engineering and Computer Science that addresses the current affairs of the college.

Energy-Related Feature Abstraction For Handwritten Digit Recognition, Thomas H. Fuller Jr.

All Computer Science and Engineering Research

Most handwritten character recognizers use either graphical (static) or first-order dynamic data. Our research speculates that the mental signal to write a digit might be partially encoded as an energy profile. We used artificial neural networks (ANN) to analyze energy-related features (first and second time derivatives) of handwritten digits of 20 subjects and later 40 subjects. An experimenal environment was developed on a NeXTstation with a real-time link to a pen-based GO computer. Although such an experiment cannot confirm an energy profile encoded in the writer, it did indicate the usefulness of energy-related features by recognizing 94.5% of the 600 …

Translation Of 'Kamalakanta: A Collection Of Satirical Essays And Reflections', Monish Ranjan Chatterjee

Electrical and Computer Engineering Faculty Publications

This venture was born initially out of the desire to make those works of Bengali literature which have moved me profoundly, and which I consider first-rate by any yardstick, available to friends and fellow enthusiasts who cannot read the original. In attempting to channel literary and philosophical masterpieces into a different medium, I Have experienced firsthand the formidable challenge that a translator must face because not only of the barrier imposed by the languages involved, but perhaps more so because .of his or her own severely inadequate faculty being called upon to match both the genius and the inspiration of …

Wright State University College Of Engineering And Computer Science Bits And Pcs Newsletter, Volume 8, Number 1, January 1992, College Of Engineering And Computer Science, Wright State University

BITs and PCs Newsletter

A ten page newsletter created by the Wright State University College of Engineering and Computer Science that addresses the current affairs of the college.

Porting The Chorus Supervisor And Related Low-Level Functions To The Pa-Risc, Ravi Konuru, Marion Hakanson, Jon Inouye, Jonathan Walpole

Computer Science Faculty Publications and Presentations

This document is part of a series of reports describing the design decisions made in porting the Chorus Operating System to the Hewlett-Packard 9000 Series 800 workstation.

The Supervisor is the name given by Chorus to a collection of low-level functions that are machine dependent and have to be implemented when Chorus is ported from one machine to another. The Supervisor is responsible for interrupt, trap and exception handling, managing low-level thread initialization, context switch, kernel initialization, managing simple devices (timer and console) and offering a low-level debugger. This document describes the port of the Supervisor and related low-level functions. …

Porting Chorus To The Pa-Risc: Overall Evaluation, Jonathan Walpole, Marion Hakanson, Jon Inouye, Ravi Konuru

Computer Science Faculty Publications and Presentations

This document is part of a series of reports describing the design decisions made in porting the Chorus Operating System kernel to the Hewlett-Packard 9000 Series 800 workstation. This document summarizes the matches and mis-matches between Chorus and the PA-RISC and outlines the general lessons learned during the project.

This document is intended for people who are interested in (a) the separation of machinedependent micro-kernel code from machine-independent micro-kernel code, (b) the interaction between operating system design and the PA-RISC architecture, and (c) the portability ofthe Chorus operating system.

The first report in the series, Porting Chorus to the PA-RISe: …

Porting Chorus To The Pa-Risc: Booting, Jon Inouye, Ravi Konuru, Jonathan Walpole, Marion Hakanson

Computer Science Faculty Publications and Presentations

We started out with the low level Tut (HP-CX 2.0) boot code. One of our goals was to reuse as much of this code as possible, which would reduce the amount of low level code we would have to debug. This was very important, especially fiince the RP 9000/834 has a very complex I/O architecture and we lacked any sophisticated debugging tools. Writing the PA-Chorus boot code involved modifying the Tut code to match the Chorus startup sequence. In the remainder of this section, we present an overview of the PA-RISC boot mechanisms and the Chorus startup sequence. Sectlon 2 …

Porting Chorus To The Pa-Risc: Building, Debugging, Testing And Validation, Ravi Konuru, Marion Hakanson, Jon Inouye, Jonathan Walpole

Computer Science Faculty Publications and Presentations

This document is part of a series of reports describing the design decisions made in porting the Chorus Operating System to the Hewlett-Packard 9000 Series 800 workstation. This document describes the environment for building the Chorus kernel, the various kernel tests, and the debugging environment used for porting the Chorus operating system to the HP PA-RISC.

The information contained in this paper will be of interest to people who wish to:

• Use the PA-Chorus kernel for development and/or modification, • Know about the build environment for Chorus kernel on PA-RISC, • Know about the PA-Chorus approach to debugging, • …

Porting Chorus To The Pa-Risc: Project Overview, Jonathan Walpole, Marion Hakanson, Jon Inouye, Ravi Konuru

Computer Science Faculty Publications and Presentations

This document is part of a series of reports describing the design decisions made in porting the Chorus Operating System to the Hewlett-Packard 9000 Series 800 workstation. This document presents an overview of the project, and outlines the other reports in the series and the relationships between them.

Porting Chorus To The Pa-Risc: Virtual Memory Manager, Jon Inouye, Marion Hakanson, Ravi Konuru, Jonathan Walpole

Computer Science Faculty Publications and Presentations

This document describes the port ofthe Chorus virtual memory manager to the Hewlett-Packard Precision Architecture rusc (PA-RISC) workstation. The information contained in this paper will be of interest to people who:

• intend to port the Chorus virtual memory section. • intend to port a virtual memory design to the Hewlett-Packard PA-RISC.

The reader is strongly encouraged to read the following PA-Chorus documents before reading this document:

• Technical Report CSE-92-3, Porting Chorus to the PA-RISC: Project Overview

High Performance Memory System Pct:Ep0199134, Robert Iannucci

Robert A Iannucci

No abstract provided.

Parallel Implementation Of Vhdl Simulations On The Intel Ipsc/2 Hypercube, Ronald C. Comeau

Theses and Dissertations

VHDL models are executed sequentially in current commercial simulators. As chip designs grow larger and more complex, simulations must run faster. One approach to increasing simulation speed is through parallel processors. This research transforms the behavioral and structural models created by Intermetrics' sequential VHDL simulator into models for parallel execution. The models are simulated on an Intel iPSC/2 hypercube with synchronization of the nodes being achieved by utilizing the Chandy Misra paradigm for discrete-event simulations. Three eight-bit adders, the ripple carry, the carry save, and the carry-lookahead, are each run through the parallel simulator. Simulation time is cut in at …

Logic Programming In Digital Circuit Design, Joseph W. Eicher

Theses and Dissertations

The design of large, complex digital circuitry requires highly skilled engineers. Much of the time spent by these engineers in the design phase involves tasks that are repetitive, tedious, and slow. If these repetitive tasks are automated, the engineer can spend more time managing the design process and produce a better-quality design in less time. Logic programming can be used to automate design tasks, even those that require a high degree of skill. This thesis investigates several aspects of the digital circuit design process that involve pattern-matching paradigms suitable for encoding in the logic programming language Prolog.